Dynamic random access memories are generally formed of a matrix of bit lines and word lines with memory cells located adjacent the intersections of the bit lines and word lines. The memory cells are enabled to provide their stored bits to the bit lines or to permit a write operation by signals carried on the word lines.
Each memory cell is typically formed of a bit storage capacitor connected to a reference voltage and through the source-drain circuit of an "access" field effect transistor to an associated bit line. The gate of the field effect transistor is connected to the word line. A logic signal carried by the word line enables the transistor, thus allowing charge to flow through the source-drain circuit of the transistor to the capacitor, or allowing charge stored on the capacitor to pass through the source-drain circuit of the access transistor to the bit line.
In order for the logic level V.sub.dd potential from the bit line to be stored on the capacitor, the word line must be driven to a voltage above V.sub.dd +V.sub.tn, where V.sub.tn is the threshold voltage of the access transistor including the effects of back bias.
During the early days of DRAM design, NMOS type FETs, that is, N-channel devices were used exclusively. In order to pass a V.sub.dd +V.sub.tn level signal to the selected word line, the gate of the pass transistor had to be driven to at least V.sub.dd +2V.sub.tn. Furthermore, to allow sufficient drive to achieve a voltage greater than V.sub.dd +V.sub.tn on the word line within a reasonable length of time in order to facilitate a relatively fast memory, the gate of the pass transistor is driven to a significantly higher voltage. In such devices, the word line driving signal utilized capacitors in a well-known double-boot strap circuit.
In the above circuit, the boot strapping voltage circuit is designed to exceed the voltage V.sub.dd +2V.sub.tn, in order to ensure that temperature, power supply, and process variations would never allow the pass transistor driving voltage to fall below V.sub.dd +2V.sub.tn.
However, it has been found that in small geometry VLSI memories, the high voltages provided by the boot-strap circuits can exceed the tolerable voltages in the memory, thus adversely affecting reliability.